반응형 파이프라인1 7. ARM 5stage pipeline report 1 [Computer Architecture] 7.1. Module description Goal : Detailed explanation for each module of the processor we implemented [Provided circuit diagram analysis and modification] [Most important point to consider] 1. Each stage has 1 clock cycle time. (In other words, the MODULE_armreduced output pc update and pipeline registers use the same edge.) Therefore, the 15th block of reg[31:0] registers[15:0] of MODULE_Register.. 2021. 12. 2. 이전 1 다음 반응형
