반응형 verilog4 7. ARM 5stage pipeline report 1 [Computer Architecture] 7.1. Module description Goal : Detailed explanation for each module of the processor we implemented [Provided circuit diagram analysis and modification] [Most important point to consider] 1. Each stage has 1 clock cycle time. (In other words, the MODULE_armreduced output pc update and pipeline registers use the same edge.) Therefore, the 15th block of reg[31:0] registers[15:0] of MODULE_Register.. 2021. 12. 2. 3. Project 3_Calculator [Logic Design] 3.1. Probelm In this problem, you will implement a mini-calculator in Verilog HDL with the attached file (calculator.v), by filling out the missing parts of the modules below. The top module is 'calculator'. There are 3 inputs for the 'calculator' module: two 2-bit operands, and one 7-bit operator. For example, in "3 + 2", "3" and "2" are operands, and "+" is operator. There is only one 4-bit ou.. 2021. 12. 2. 2. Project 2_Missionaries and cannibals problem [Logic Design] 2.1. Problem Three missionaries and three cannibals must cross a river. They cross the river using a boat which can carry at most two people. On each side of the river, cannibals must not outnumber missionaries, otherwise cannibals will eat missionaries. Order Left Boat Right 0 MMM CCC 1 MMMC CC -> CC 2 MMMCC CCC 4 MMMC MM CC 6 MMCC MMM C 8 CCC MMM CC 10 CC MMM CCC Implement sequential logic of .. 2021. 12. 2. 1. Project 1_Missionaries and cannibals problem [Logic Design] 1.1. Problem Three missionaries and three cannibals must cross a river. They cross the river using a boat which can carry at most two people. On each side of the river, cannibals must not outnumber missionaries, otherwise cannibals will eat missionaries. Order Left Boat Right 0 MMM CCC 1 MMMC CC -> CC 2 MMMCC CCC 4 MMMC MM CC 6 MMCC MMM C 8 CCC MMM CC 10 CC MMM CCC Implement combinational logic .. 2021. 12. 1. 이전 1 다음 반응형
