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8.1. Code
# 아래 code는 부정행위 방지를 위해 정상 동작하지 않도록 일부 수정된 code입니다. 따라서 정상 작동하지 않는 code임을 유의하여 주시기 바랍니다.
module ExtendMUX(
input[23:0] in,
input[1:0] ImmSrc,
input PC_Stall,
output reg[31:0] ExtImm
);
integer i;
always @ (*)
begin
if(PC_Stall == 1'b0) begin
case(ImmSrc)
2'b00:
begin
ExtImm[7:0] = in[7:0];
for(i=8;i<32;i=i+1)
ExtImm[i] = in[7];
end
2'b01:
begin
ExtImm[11:0] = in[11:0];
for(i=12;i<32;i=i+1)
ExtImm[i] = 'b0;
end
2'b10:
begin
ExtImm[1:0] = 2'b00;
ExtImm[25:2] = in[23:0];
for(i=26;i<32;i=i+1)
ExtImm[i] = in[23];
end
default:
ExtImm = 'h00000000;
endcase
end
end
endmodule
module RegisterFile(
input EX_PCSrc,
input PC_Stall,
input clk,
input reset,
input we,
input[1:0] RegSrc,
input[3:0] addr1,
input[3:0] addr2,
input[3:0] addr3,
input[3:0] waddr,
input[31:0] wdata,
input[31:0] pcin,
/*
output reg[31:0] data1,
output reg[31:0] data2,
output reg[31:0] data3,
*/
output[31:0] data1,
output[31:0] data2,
output[31:0] data3,
output[31:0] pcout
);
reg[31:0] registers[15:0];
reg[31:0] pcregister;
integer idx;
//assign pcout = registers[15];
assign pcout = pcregister;
// write to register file
always @ (negedge clk) begin
if (reset) begin
for(idx=0; idx<=14; idx=idx+1) begin //idx<=15 :원래 싱글사이클s
registers[idx] = 'h00000000;
end
end
else begin
if(we) begin
if((RegSrc[0] != 1'b1) && (EX_PCSrc == 1'b1) && (waddr != 4'd15))
registers[waddr] = wdata;
else
registers[14] = pcregister + 'd4;
end
/*
if (waddr != 4'b1111 || RegSrc[0] == 1'b1 )
registers[15] = pcin;
end
*/
end
end
// read from register file
/*
always @ (posedge clk) begin
if (reset) begin
data1 <= 'h00000000;
data2 <= 'h00000000;
end
else begin
if (addr1 == 15) begin
data1 = pcregister + 32'd8;
end
else begin
data1 = registers[addr1];
end
if (addr2 == 15) begin
data2 = pcregister + 32'd8;
end
else begin
// RegSrc MUX
if (RegSrc[1] == 1'b0)
data2 = registers[addr2];
else
data2 = registers[waddr];
end
if (addr3 == 15) begin
data3 = pcregister + 32'd8;
end
else begin
data3 = registers[addr3];
end
end
if ((waddr != 4'b1111 || RegSrc[0] == 1'b1) && (PC_Stall == 1'b0)) begin
pcregister = pcin;
end
end
*/
assign data1 = (reset == 1'b1) ? 'h00000000 :
(addr1 == 15) ? pcregister + 32'd8 : registers[addr1];
assign data2 = (reset == 1'b1) ? 'h00000000 :
(addr2 == 15) ? pcregister + 32'd8 :
(RegSrc[1] == 1'b0) ? registers[addr2] : registers[waddr];
assign data3 = (addr3 == 15) ? pcregister + 32'd8 : registers[addr3];
always @ (posedge clk) begin
if ((waddr != 4'b1111 || RegSrc[0] == 1'b1) && (PC_Stall == 1'b0)) begin
pcregister = pcin;
end
end
endmodule
module IF_ID_reg(
input clk,
input[31:0] inst,
input reset,
input IF_ID_reg_Stall,
input IF_ID_reg_Flush,
output reg[31:0] IF_ID_reg_inst,
output reg IF_ID_reg_reset
);
always @ (posedge clk) begin
if(IF_ID_reg_Stall == 1'b0) begin
IF_ID_reg_reset <= reset;
IF_ID_reg_inst <= inst;
end
if(IF_ID_reg_Flush == 1'b1) begin
IF_ID_reg_reset <= 1'd0;
IF_ID_reg_inst <= 32'd0;
end
end
endmodule
module ID_EX_reg(
input clk,
input[3:0] ID_NZCV_Flags,
input ID_reset,
input[31:0] ID_WriteAddr,
input[3:0] ID_ALUOp,
input[1:0] ID_ImmSrc,
input[1:0] ID_RegSrc,
input ID_PCSrc,
input ID_RegWrite,
input ID_MemWrite,
input ID_MemtoReg,
input ID_ALUSrc,
input ID_Svalue,
input[31:0] ID_ReadData1,
input[31:0] ID_ReadData2,
input[31:0] ID_ReadData3,
input[31:0] ID_ExtImm,
input[3:0] ID_ReadAddr1,
input[3:0] ID_ReadAddr2,
input[31:0] ID_inst,
input ID_EX_reg_Flush,
input ID_EX_reg_Stall,
input[31:0] PCtmptmp,
output reg ID_EX_reg_reset,
output reg[3:0] ID_EX_reg_ALUOp,
output reg[1:0] ID_EX_reg_ImmSrc,
output reg[1:0] ID_EX_reg_RegSrc,
output reg ID_EX_reg_PCSrc,
output reg ID_EX_reg_RegWrite,
output reg ID_EX_reg_MemWrite,
output reg ID_EX_reg_MemtoReg,
output reg ID_EX_reg_ALUSrc,
output reg ID_EX_reg_Svalue,
output reg[31:0] ID_EX_reg_Readdata1,
output reg[31:0] ID_EX_reg_Readdata2,
output reg[31:0] ID_EX_reg_Readdata3,
output reg[31:0] ID_EX_reg_ExtImm,
output reg[31:0] ID_EX_reg_WriteAddr,
output reg[3:0] ID_EX_reg_NZCV_Flags,
output reg[3:0] ID_EX_reg_ReadAddr1,
output reg[3:0] ID_EX_reg_ReadAddr2,
output reg[31:0] ID_EX_reg_inst,
output reg[31:0] ID_EX_reg_PCtmptmp
);
always @ (posedge clk) begin
if(ID_EX_reg_Stall == 1'b0) begin
ID_EX_reg_reset <= ID_reset;
ID_EX_reg_ALUOp <= ID_ALUOp;
ID_EX_reg_ImmSrc <= ID_ImmSrc;
ID_EX_reg_RegSrc <= ID_RegSrc;
ID_EX_reg_PCSrc <= ID_PCSrc;
ID_EX_reg_RegWrite <= ID_RegWrite;
ID_EX_reg_MemWrite <= ID_MemWrite;
ID_EX_reg_MemtoReg <= ID_MemtoReg;
ID_EX_reg_ALUSrc <= ID_ALUSrc;
ID_EX_reg_Svalue <= ID_Svalue;
ID_EX_reg_Readdata1 <= ID_ReadData1;
ID_EX_reg_Readdata2 <= ID_ReadData2;
ID_EX_reg_Readdata3 <= ID_ReadData3;
ID_EX_reg_ExtImm <= ID_ExtImm;
ID_EX_reg_NZCV_Flags <= ID_NZCV_Flags;
ID_EX_reg_WriteAddr <= ID_WriteAddr;
ID_EX_reg_ReadAddr1 <= ID_ReadAddr1;
ID_EX_reg_ReadAddr2 <= ID_ReadAddr2;
ID_EX_reg_inst <= ID_inst;
ID_EX_reg_PCtmptmp <= PCtmptmp;
end
if((ID_EX_reg_Flush == 1'b1) && (ID_EX_reg_Stall == 1'b0)) begin
ID_EX_reg_reset <= 1'd0;
ID_EX_reg_ALUOp <= 4'd0;
ID_EX_reg_ImmSrc <= 2'd0;
ID_EX_reg_RegSrc <= 2'd0;
ID_EX_reg_PCSrc <= 1'd0;
ID_EX_reg_RegWrite <= 1'd0;
ID_EX_reg_MemWrite <= 1'd0;
ID_EX_reg_MemtoReg <= 1'd0;
ID_EX_reg_ALUSrc <= 1'd0;
ID_EX_reg_Svalue <= 1'd0;
ID_EX_reg_Readdata1 <= 32'd0;
ID_EX_reg_Readdata2 <= 32'd0;
ID_EX_reg_Readdata3 <= 32'd0;
ID_EX_reg_ExtImm <= 32'd0;
ID_EX_reg_NZCV_Flags <= 4'd0;
ID_EX_reg_WriteAddr <= 32'd0;
ID_EX_reg_ReadAddr1 <= 4'd0;
ID_EX_reg_ReadAddr2 <= 4'd0;
ID_EX_reg_inst <= 32'd0;
ID_EX_reg_PCtmptmp <= 32'd0;
end
if(ID_reset == 1'b1) begin
ID_EX_reg_reset <= 1'd0;
ID_EX_reg_ALUOp <= 4'd0;
ID_EX_reg_ImmSrc <= 2'd0;
ID_EX_reg_RegSrc <= 2'd0;
ID_EX_reg_PCSrc <= 1'd0;
ID_EX_reg_RegWrite <= 1'd0;
ID_EX_reg_MemWrite <= 1'd0;
ID_EX_reg_MemtoReg <= 1'd0;
ID_EX_reg_ALUSrc <= 1'd0;
ID_EX_reg_Svalue <= 1'd0;
ID_EX_reg_Readdata1 <= 32'd0;
ID_EX_reg_Readdata2 <= 32'd0;
ID_EX_reg_Readdata3 <= 32'd0;
//ID_EX_reg_ExtImm <= 32'd0;
ID_EX_reg_NZCV_Flags <= 4'd0;
ID_EX_reg_WriteAddr <= 32'd0;
ID_EX_reg_ReadAddr1 <= 4'd0;
ID_EX_reg_ReadAddr2 <= 4'd0;
//ID_EX_reg_inst <= 32'd0;
end
end
/*
always @ (negedge clk) begin
if(ID_EX_reg_Flush == 1'b1) begin
ID_EX_reg_ExtImm <= 32'd0;
ID_EX_reg_PCtmptmp <= 32'd0; //여전히 고민중...
end
end
*/
endmodule
module EX_MEM_reg(
input clk,
input EX_reset,
input EX_RegWrite,
input EX_MemWrite,
input EX_MemtoReg,
input[31:0] EX_Readdata3,
input[3:0] EX_WriteAddr,
input[31:0] EX_ALUResult,
input[31:0] EX_PCBranch,
input[31:0] EX_inst,
input[31:0] EX_PCSrc,
output reg EX_MEM_reg_reset,
output reg EX_MEM_reg_RegWrite,
output reg EX_MEM_reg_MemWrite,
output reg EX_MEM_reg_MemtoReg,
output reg[31:0] EX_MEM_reg_ALUResult,
output reg[31:0] EX_MEM_reg_Readdata3, //armedreduced output writedata
output reg[3:0] EX_MEM_reg_WriteAddr, //WBstage
output reg[31:0] EX_MEM_reg_PCBranch,
output reg[31:0] EX_MEM_reg_inst,
output reg[31:0] EX_MEM_reg_PCSrc
);
always @(posedge clk) begin
EX_MEM_reg_reset <= EX_reset;
EX_MEM_reg_RegWrite <= EX_RegWrite;
EX_MEM_reg_MemWrite <= EX_MemWrite;
EX_MEM_reg_MemtoReg <= EX_MemtoReg;
EX_MEM_reg_ALUResult <= EX_ALUResult;
EX_MEM_reg_Readdata3 <= EX_Readdata3;
EX_MEM_reg_WriteAddr <= EX_WriteAddr;
EX_MEM_reg_PCBranch <= EX_PCBranch;
EX_MEM_reg_inst <= EX_inst;
EX_MEM_reg_PCSrc <= EX_PCSrc;
end
endmodule
module MEM_WB_reg(
input clk,
input MEM_reset,
input MEM_RegWrite,
input MEM_MemtoReg,
input[31:0] MEM_ALUResult,
input[31:0] MEM_Readdata,
input[31:0] MEM_WriteAddr,
output reg MEM_WB_reg_reset,
output reg MEM_WB_reg_RegWrite,
output reg MEM_WB_reg_MemtoReg,
output reg[31:0] MEM_WB_reg_ALUResult,
output reg[31:0] MEM_WB_reg_Readdata,
output reg[31:0] MEM_WB_reg_WriteAddr
);
always @(posedge clk) begin
MEM_WB_reg_reset <= MEM_reset;
MEM_WB_reg_RegWrite <= MEM_RegWrite;
MEM_WB_reg_MemtoReg <= MEM_MemtoReg;
MEM_WB_reg_ALUResult <= MEM_ALUResult;
MEM_WB_reg_Readdata <= MEM_Readdata;
MEM_WB_reg_WriteAddr <= MEM_WriteAddr;
end
endmodule
module Hazard(
input MEM_RegWrite,
input WB_RegWrite,
input EX_MemtoReg,
input[3:0] ID_ReadAddr1,
input[3:0] ID_ReadAddr2,
input[3:0] EX_ReadAddr1,
input[3:0] EX_ReadAddr2,
input[3:0] ID_WriteAddr,
input[3:0] EX_WriteAddr,
input[3:0] MEM_WriteAddr,
input[3:0] WB_WriteAddr,
input MEM_MemtoReg,
input WB_MemtoReg,
input EX_NZCV_Z,
input[31:0] ID_inst,
input[31:0] EX_inst, //inst[27:25] == 101 && inst[24] == 0
input[31:0] MEM_inst,
output reg[1:0] ForwardA,
output reg[1:0] ForwardB,
output reg[1:0] ForwardC,
output reg IF_ID_reg_Flush,
output reg ID_EX_reg_Flush,
output reg PC_Stall,
output reg IF_ID_reg_Stall
);
always @ (*) begin
PC_Stall <= 1'b0;
IF_ID_reg_Stall <= 1'b0;
ID_EX_reg_Flush <= 1'b0;
if(((ID_ReadAddr1 == EX_WriteAddr) || (ID_ReadAddr2 == EX_WriteAddr)) && (EX_MemtoReg == 1'b1) ) begin //LW
PC_Stall <= 1'b1;
IF_ID_reg_Stall <= 1'b1;
ID_EX_reg_Flush <= 1'b1;
end
ForwardA <= 2'b00;
ForwardB <= 2'b00;
if((WB_WriteAddr == MEM_WriteAddr) && (MEM_WriteAddr == EX_ReadAddr1) && (MEM_RegWrite == 1'b1)) begin
ForwardA <= 2'b10;
end
if((WB_WriteAddr == MEM_WriteAddr) && (MEM_WriteAddr == EX_ReadAddr2) && (MEM_RegWrite == 1'b1)) begin
ForwardB <= 2'b10;
end
if((WB_WriteAddr == EX_ReadAddr1) && (WB_RegWrite == 1'b1)) begin
ForwardA <= 2'b01;
end
if((WB_WriteAddr == EX_ReadAddr2) && (WB_RegWrite == 1'b1)) begin
ForwardB <= 2'b01;
end
if((MEM_WriteAddr == EX_ReadAddr1) && (MEM_RegWrite == 1'b1)) begin
ForwardA <= 2'b10;
end
if((MEM_WriteAddr == EX_ReadAddr2) && (MEM_RegWrite == 1'b1)) begin
ForwardB <= 2'b10;
end
if((MEM_WriteAddr == EX_WriteAddr) && (MEM_RegWrite == 1'b1)) begin
ForwardC <= 2'b01;
end
if((WB_WriteAddr == EX_WriteAddr) && (WB_RegWrite == 1'b1)) begin
ForwardC <= 2'b10;
end
/*
if((WB_WriteAddr == ID_WriteAddr) && (WB_MemtoReg == 1'b1)) begin
ForwardC <= 2'b01;
end
if((MEM_WriteAddr == ID_WriteAddr) && (MEM_MemtoReg == 1'b1)) begin
ForwardC <= 2'b10;
end
*/
/*
ForwardA <= 2'b00;
ForwardB <= 2'b00;
if(MEM_RegWrite == 1'b1) begin
if(EX_ReadAddr1 == WB_WriteAddr) begin
ForwardA <= 2'b01;
end
if(EX_ReadAddr2 == WB_WriteAddr) begin
ForwardB <= 2'b01;
end
end
if(MEM_RegWrite == 1'b1) begin
if(EX_ReadAddr1 == MEM_WriteAddr) begin
ForwardA <= 2'b10;
end
if(EX_ReadAddr2 == MEM_WriteAddr) begin
ForwardB <= 2'b10;
end
end
*/
IF_ID_reg_Flush <= 1'b0;
ID_EX_reg_Flush <= 1'b0;
if(((EX_NZCV_Z == 1'b1) && (EX_inst[27:25] == 3'b101) && (EX_inst[24] == 1'b1)) || ((MEM_inst[27:25] == 3'b101) && (MEM_inst[24] == 1'b0))) begin
IF_ID_reg_Flush <= 1'b1;
ID_EX_reg_Flush <= 1'b1;
end
end
endmodule
module Select(
input[1:0] ForwardA,
input[1:0] ForwardB,
input[1:0] ForwardC,
input[31:0] EX_Readdata1,
input[31:0] EX_Readdata2,
input[31:0] EX_Readdata3,
input[31:0] WB_Result,
input[31:0] MEM_ALUResult,
/*
output reg[31:0] EX_reg_Readdata1,
output reg[31:0] EX_reg_Readdata2,
output reg[31:0] EX_reg_Readdata3
*/
output[31:0] EX_temp_Readdata1,
output[31:0] EX_temp_Readdata2,
output[31:0] EX_temp_Readdata3
);
/*
always @ (*) begin
EX_reg_Readdata1 <= EX_Readdata1;
if(ForwardA == 2'b01) begin
EX_reg_Readdata1 <= WB_Result;
end
if(ForwardA == 2'b10) begin
EX_reg_Readdata1 <= MEM_ALUResult;
end
EX_reg_Readdata2 <= EX_Readdata1;
if(ForwardB == 2'b01) begin
EX_reg_Readdata2 <= WB_Result;
end
if(ForwardB == 2'b10) begin
EX_reg_Readdata2 <= MEM_ALUResult;
end
EX_reg_Readdata3 <= EX_Readdata1;
if(ForwardC == 2'b01) begin
EX_reg_Readdata3 <= WB_Result;
end
if(ForwardC == 2'b10) begin
EX_reg_Readdata3 <= MEM_ALUResult;
end
end*/
assign EX_temp_Readdata1 = (ForwardA == 2'b01) ? WB_Result :
(ForwardA == 2'b10) ? MEM_ALUResult :
EX_Readdata1;
assign EX_temp_Readdata2 = (ForwardB == 2'b01) ? WB_Result :
(ForwardB == 2'b10) ? MEM_ALUResult :
EX_Readdata1;
assign EX_temp_Readdata3 = (ForwardC == 2'b01) ? WB_Result :
(ForwardC == 2'b10) ? MEM_ALUResult :
EX_Readdata1;
endmodule
module SelectPC(
input[3:0] cond,
input EX_PCSrc,
input[3:0] EX_ALUFlags,
input[31:0] MEM_PCBranch,
input[31:0] PCPlus4,
output[31:0] PCtmp
);
assign PCtmp = (((cond == 4'b1110) && (EX_PCSrc == 1'b1)) || ((cond == 4'b0000) && (EX_ALUFlags[2] == 1'b1) && (EX_PCSrc == 1'b1)) || ((cond == 4'b0001) && (EX_ALUFlags[2] == 1'b0) && (EX_PCSrc == 1'b1))) ? MEM_PCBranch : PCPlus4;
endmodule
module armreduced(
input clk,
input reset,
output[31:0] pc,
input[31:0] inst,
input nIRQ,
output[3:0] be,
output[31:0] memaddr,
output memwrite,
output memread,
output[31:0] writedata,
input[31:0] readdata
);
//1111 0001 1010 0000 0000 0000 0000 0000
assign be = 4'b1111;
//Hazard
wire[1:0] ForwardA;
wire[1:0] ForwardB;
wire[1:0] ForwardC;
wire IF_ID_reg_Flush;
wire ID_EX_reg_Flush;
wire PC_Stall;
wire IF_ID_reg_Stall;
wire ID_reset;
wire[31:0] ID_inst;
//wire[31:0] ID_PCPlus4;
wire[3:0] ID_ReadAddr1, ID_ReadAddr2;
wire[31:0] ID_ReadData1, ID_ReadData2, ID_ReadData3;
wire[31:0] ID_Result, ID_ExtImm, ID_SrcB, ID_ALUResult;
wire[3:0] ID_ALUOp, ID_ALUFlags;
wire[1:0] ID_RegSrc, ID_ImmSrc;
wire ID_PCSrc, ID_RegWrite, ID_MemWrite, ID_MemtoReg, ID_ALUSrc, ID_Svalue;
wire[3:0] ID_NZCV_Flags;
reg[3:0] NZCV;
wire EX_reset;
wire[3:0] EX_ALUOp;
wire[1:0] EX_ImmSrc;
wire[1:0] EX_RegSrc;
wire EX_PCSrc;
wire EX_RegWrite;
wire EX_MemWrite;
wire EX_MemtoReg;
wire EX_ALUSrc;
wire EX_Svalue;
wire[31:0] EX_Readdata1;
wire[31:0] EX_Readdata2;
wire[31:0] EX_Readdata3;
wire[31:0] EX_ExtImm;
wire[3:0] EX_WriteAddr;
wire[31:0] EX_SrcB;
wire[31:0] EX_ALUFlags;
wire[31:0] EX_ALUResult;
wire[31:0] EX_inst;
wire[3:0] EX_ReadAddr1;
wire[3:0] EX_ReadAddr2;
wire MEM_reset;
wire MEM_RegWrite;
wire MEM_MemWrite;
wire MEM_MemtoReg;
wire[31:0] MEM_ALUResult;
wire[31:0] MEM_Readdata3;
wire[31:0] MEM_WriteAddr;
wire WB_reset;
wire WB_RegWrite;
wire WB_MemtoReg;
wire[31:0] WB_ALUResult;
wire[31:0] WB_Readdata;
wire[3:0] WB_WriteAddr;
wire[31:0] PCtmp;
wire[31:0] PCPlus4;
wire[31:0] PCBranch;
wire[31:0] PCtmptmp;
wire[31:0] MEM_PCBranch;
wire[31:0] MEM_inst;
wire[31:0] PC;
//Hazard
Hazard _Hazrd(
.MEM_RegWrite(MEM_RegWrite),
.WB_RegWrite(WB_RegWrite),
.EX_MemtoReg(EX_MemtoReg),
.ID_ReadAddr1(ID_ReadAddr1),
.ID_ReadAddr2(ID_ReadAddr2),
.EX_ReadAddr1(EX_ReadAddr1),
.EX_ReadAddr2(EX_ReadAddr2),
.ID_WriteAddr(ID_WriteAddr),
.EX_WriteAddr(EX_WriteAddr),
.MEM_WriteAddr(MEM_WriteAddr),
.WB_WriteAddr(WB_WriteAddr),
.MEM_MemtoReg(MEM_MemtoReg),
.WB_MemtoReg(WB_MemtoReg),
.EX_NZCV_Z(NZCV[2]),
.ID_inst(ID_inst),
.EX_inst(EX_inst), //inst[27:25] == 101 && inst[24] == 0
.MEM_inst(MEM_inst),
.ForwardA(ForwardA),
.ForwardB(ForwardB),
.ForwardC(ForwardC),
.IF_ID_reg_Flush(IF_ID_reg_Flush),
.ID_EX_reg_Flush(ID_EX_reg_Flush),
.PC_Stall(PC_Stall),
.IF_ID_reg_Stall(IF_ID_reg_Stall)
);
//IF STAGE
/* //*
always @(posedge clk) begin
if(PC_Stall == 1'b0) begin
PC <= PCtmp;
end
end
*/
/*
always @(*) begin
PC <= PCtmp;
end
*/
assign PC = PCtmp;
IF_ID_reg _IF_ID_reg(
.clk(clk),
.inst(inst),
.reset(reset),
.IF_ID_reg_Stall(IF_ID_reg_Stall),
.IF_ID_reg_Flush(IF_ID_reg_Flush),
.IF_ID_reg_inst(ID_inst),
.IF_ID_reg_reset(ID_reset)
);
//ID STAGE
assign ID_ReadAddr1 = ID_inst[19:16];
assign ID_ReadAddr2 = ID_inst[3:0];
assign ID_WriteAddr = ID_inst[15:12];
ctrlSig _ctrlSig(
.NZCV(NZCV), .cond(ID_inst[31:28]), .op(ID_inst[27:26]), .funct(ID_inst[25:20]), .ALUOp(ID_ALUOp), .ImmSrc(ID_ImmSrc), .RegSrc(ID_RegSrc),
.PCSrc(ID_PCSrc), .RegWrite(ID_RegWrite), .MemWrite(ID_MemWrite), .MemtoReg(ID_MemtoReg), .ALUSrc(ID_ALUSrc), .Svalue(ID_Svalue));
/* //*
RegisterFile _RegisterFile( .clk(clk), .reset(ID_reset), .we(ID_RegWrite), .RegSrc(ID_RegSrc), .addr1(ID_ReadAddr1), .addr2(ID_ReadAddr2), .addr3(ID_WriteAddr),
.waddr(WB_WriteAddr), .wdata(WB_Result), .pcin(PCPlus4), .data1(ID_ReadData1), .data2(ID_ReadData2), .data3(ID_ReadData3), .pcout(PCtmptmp));
*/
RegisterFile _RegisterFile( .EX_PCSrc(EX_PCSrc), .PC_Stall(PC_Stall), .clk(clk), .reset(ID_reset), .we(ID_RegWrite), .RegSrc(ID_RegSrc), .addr1(ID_ReadAddr1), .addr2(ID_ReadAddr2), .addr3(ID_WriteAddr),
.waddr(WB_WriteAddr), .wdata(WB_Result), .pcin(PC), .data1(ID_ReadData1), .data2(ID_ReadData2), .data3(ID_ReadData3), .pcout(PCtmptmp));
ExtendMUX _ExtendMUX(.PC_Stall(PC_Stall), .in(ID_inst[23:0]), .ImmSrc(ID_ImmSrc), .ExtImm(ID_ExtImm) );
//aasgin pc = pctmptmp;
//assign pc = (((cond == 4'b1110) && (EX_PCSrc == 1'b1)) || ((cond == 4'b0000) && (EX_ALUFlags[2] == 1'b1) && (EX_PCSrc == 1'b1)) || ((cond == 4'b0001) && (EX_ALUFlags[2] == 1'b0) && (EX_PCSrc == 1'b1))) ? PCBranch : PCtmptmp; //armreduced output
assign pc = PCtmp;
wire[31:0] EX_PCtmptmp;
ID_EX_reg _ID_EX_reg(
.clk(clk),
.ID_NZCV_Flags(ID_NZCV_Flags),
.ID_reset(ID_reset),
.ID_WriteAddr(ID_WriteAddr),
.ID_ALUOp(ID_ALUOp),
.ID_ImmSrc(ID_ImmSrc),
.ID_RegSrc(ID_RegSrc),
.ID_PCSrc(ID_PCSrc),
.ID_RegWrite(ID_RegWrite),
.ID_MemWrite(ID_MemWrite),
.ID_MemtoReg(ID_MemtoReg),
.ID_ALUSrc(ID_ALUSrc),
.ID_Svalue(ID_Svalue),
.ID_ReadData1(ID_ReadData1),
.ID_ReadData2(ID_ReadData2),
.ID_ReadData3(ID_ReadData3),
.ID_ExtImm(ID_ExtImm),
.ID_ReadAddr1(ID_ReadAddr1),
.ID_ReadAddr2(ID_ReadAddr2),
.ID_inst(ID_inst),
.ID_EX_reg_Flush(ID_EX_reg_Flush),
.ID_EX_reg_Stall(ID_EX_reg_Stall),
.PCtmptmp(PCtmptmp),
.ID_EX_reg_reset(EX_reset),
.ID_EX_reg_ALUOp(EX_ALUOp),
.ID_EX_reg_ImmSrc(EX_ImmSrc),
.ID_EX_reg_RegSrc(EX_RegSrc),
.ID_EX_reg_PCSrc(EX_PCSrc),
.ID_EX_reg_RegWrite(EX_RegWrite),
.ID_EX_reg_MemWrite(EX_MemWrite),
.ID_EX_reg_MemtoReg(EX_MemtoReg),
.ID_EX_reg_ALUSrc(EX_ALUSrc),
.ID_EX_reg_Svalue(EX_Svalue),
.ID_EX_reg_Readdata1(EX_Readdata1),
.ID_EX_reg_Readdata2(EX_Readdata2),
.ID_EX_reg_Readdata3(EX_Readdata3),
.ID_EX_reg_ExtImm(EX_ExtImm),
.ID_EX_reg_WriteAddr(EX_WriteAddr),
.ID_EX_reg_NZCV_Flags(EX_NZCV_Flags),
.ID_EX_reg_ReadAddr1(EX_ReadAddr1),
.ID_EX_reg_ReadAddr2(EX_ReadAddr2),
.ID_EX_reg_inst(EX_inst),
.ID_EX_reg_PCtmptmp(EX_PCtmptmp)
);
//EX STAGE
//always @ (negedge clk) begin
//if(EX_reset == 1'b1) begin
// PCBranch <= 32'd0;
//end
//else begin
assign PCBranch = EX_PCtmptmp + EX_ExtImm + 32'd8;
//end
//end
//assign PCtmp = (EX_PCSrc == 1'b0) ? PCPlus4 : PCBranch;
//assign PCtmp = ((EX_ALUFlags[2] == 1'b1) && (EX_PCSrc == 1'b1) || ) ? PCBranch : PCPlus4;
wire[3:0] cond;
assign cond = MEM_inst[31:28];
assign PCPlus4 = PCtmptmp + 32'd4;
/*
assign PCtmp = (((cond == 4'b1110) && (EX_PCSrc == 1'b1)) || ((cond == 4'b0000) && (EX_ALUFlags[2] == 1'b1) && (EX_PCSrc == 1'b1)) || ((cond == 4'b0001) && (EX_ALUFlags[2] == 1'b0) && (EX_PCSrc == 1'b1))) ? MEM_PCBranch : PCPlus4;
*/
SelectPC _SelectPC(
.cond(cond),
.EX_PCSrc(EX_PCSrc),
.EX_ALUFlags(EX_ALUFlags),
.MEM_PCBranch(MEM_PCBranch),
.PCPlus4(PCPlus4),
.PCtmp(PCtmp)
);
always @(negedge clk) begin
if (EX_reset) NZCV = 4'b0000;
else NZCV = (EX_Svalue == 1'b1) ? EX_ALUFlags : EX_NZCV_Flags;
end
/*
always @ (*) begin
if(ForwardA == 2'b01) begin
assign EX_Readdata1 = WB_Result;
end
if(ForwardA == 2'b10) begin
assign EX_Readdata1 = MEM_ALUResult;
end
if(ForwardB == 2'b01) begin
assign EX_Readdata2 = WB_Result;
if(ForwardB == 2'b10) begin
assign EX_Readdata2 = MEM_ALUResult;
end
if(ForwardA == 2'b01) begin
assign EX_Readdata3 = WB_Result;
end
if(ForwardA == 2'b10) begin
assign EX_Readdata3 = MEM_ALUResult;
end
end
*/
wire[31:0] EX_temp_Readdata1;
wire[31:0] EX_temp_Readdata2;
wire[31:0] EX_temp_Readdata3;
Select _Select(
.ForwardA(ForwardA),
.ForwardB(ForwardB),
.ForwardC(ForwardC),
.EX_Readdata1(EX_Readdata1),
.EX_Readdata2(EX_Readdata2),
.EX_Readdata3(EX_Readdata3),
.WB_Result(WB_Result),
.MEM_ALUResult(MEM_ALUResult),
.EX_temp_Readdata1(EX_temp_Readdata1),
.EX_temp_Readdata2(EX_temp_Readdata2),
.EX_temp_Readdata3(EX_temp_Readdata3)
);
/*
assign EX_Readdata1 = (ForwardA == 2'b01) ? WB_Result : ((ForwardA == 2'b10) ? MEM_ALUResult : EX_Readdata1);
assign EX_Readdata2 = (ForwardB == 2'b01) ? WB_Result : ((ForwardB == 2'b10) ? MEM_ALUResult : EX_Readdata2);
assign EX_Readdata3 = (ForwardC == 2'b01) ? WB_Result : ((ForwardC == 2'b10) ? MEM_ALUResult : EX_Readdata3);
*/
assign EX_SrcB = (EX_ALUSrc == 1'b0) ? EX_temp_Readdata2 : EX_ExtImm;
ALU32bit _ALU32bit( .SrcA(EX_temp_Readdata1), .SrcB(EX_SrcB), .ALUOp(EX_ALUOp), .ALUFlags(EX_ALUFlags), .ALUResult(EX_ALUResult) );
EX_MEM_reg _EX_MEM_reg(
.clk(clk),
.EX_reset(EX_reset),
.EX_RegWrite(EX_RegWrite),
.EX_MemWrite(EX_MemWrite),
.EX_MemtoReg(EX_MemtoReg),
.EX_ALUResult(EX_ALUResult),
.EX_Readdata3(EX_reg_Readdata3),
.EX_WriteAddr(EX_WriteAddr),
.EX_PCBranch(PCBranch),
.EX_inst(EX_inst),
.EX_PCSrc(EX_PCSrc),
.EX_MEM_reg_reset(MEM_reset),
.EX_MEM_reg_RegWrite(MEM_RegWrite),
.EX_MEM_reg_MemWrite(MEM_MemWrite),
.EX_MEM_reg_MemtoReg(MEM_MemtoReg),
.EX_MEM_reg_ALUResult(MEM_ALUResult),
.EX_MEM_reg_Readdata3(MEM_Readdata3),
.EX_MEM_reg_WriteAddr(MEM_WriteAddr),
.EX_MEM_reg_PCBranch(MEM_PCBranch),
.EX_MEM_reg_inst(MEM_inst),
.EX_MEM_reg_PCSrc(MEM_PCSrc)
);
//MEM STAGE
assign writedata = MEM_Readdata3; //armreduced output
assign memaddr = MEM_ALUResult; //armreduced output
assign memwrite = MEM_MemWrite; //armreduced output
assign memread = 1'b1; //armreduced output
assign MEM_Readdata = readdata; //armreduced input
MEM_WB_reg _MEM_WB_reg(
.clk(clk),
.MEM_reset(MEM_reset),
.MEM_RegWrite(MEM_RegWrite),
.MEM_MemtoReg(MEM_MemtoReg),
.MEM_ALUResult(MEM_ALUResult),
.MEM_Readdata(MEM_Readdata),
.MEM_WriteAddr(MEM_WriteAddr),
.MEM_WB_reg_reset(WB_reset),
.MEM_WB_reg_RegWrite(WB_RegWrite),
.MEM_WB_reg_MemtoReg(WB_MemtoReg),
.MEM_WB_reg_ALUResult(WB_ALUResult),
.MEM_WB_reg_Readdata(WB_Readdata),
.MEM_WB_reg_WriteAddr(WB_WriteAddr)
);
//WB STAGE
assign WB_Result = (WB_MemtoReg == 1'b0) ? WB_ALUResult : WB_Readdata;
endmodule반응형
/*
module IFstage(
input clk,
input[31:0] inst,
input reset,
//input[31:0] pc,
|
//output reg IF_ID_reg_pctmp,
output reg[31:0] IF_ID_reg_inst,
//output reg[31:0] IF_ID_reg_PCPlus4,
output reg IF_ID_reg_reset
);
//assign pc = pctmp;
//assign PCPlus4 = pctmp + 32'd4;
always @ (posedge clk) begin
IF_ID_reg_reset <= reset;
IF_ID_reg_inst <= inst;
//IF_ID_reg_PCPlus4 <= PCPlus4;
//IF_ID_reg_pctmp <= pctmp;
end
endmodule
module IDstage(
input clk,
input NZCV_Flags,
input IF_ID_reg_reset,
input IF_ID_reg_inst,
//input IF_ID_reg_PCPlus4,
//input IF_ID_reg_pctmp,
input WriteAddr,
input[31:0] NextPC,
output[31:0] pctmp,
output reg ID_EX_reg_reset,
output reg[3:0] ID_EX_reg_ALUOp,
output reg[1:0] ID_EX_reg_ImmSrc,
output reg[1:0] ID_EX_reg_RegSrc,
output reg ID_EX_reg_PCSrc,
output reg ID_EX_reg_RegWrite,
output reg ID_EX_reg_MemWrite,
output reg ID_EX_reg_MemtoReg,
output reg ID_EX_reg_ALUSrc,
output reg ID_EX_reg_Svalue,
output reg[31:0] ID_EX_reg_Readdata1,
output reg[31:0] ID_EX_reg_Readdata2,
output reg[31:0] ID_EX_reg_Readdata3,
//output reg[31:0] ID_EX_reg_pcout,
output reg[31:0] ID_EX_reg_ExtImm,
//output reg[31:0] ID_EX_reg_PCPlus4,
output reg[31:0] ID_EX_reg_WriteAddr,
output reg[3:0] ID_EX_reg_NZCV_Flags,
);
wire[3:0] ReadAddr1, ReadAddr2;
wire[31:0] ReadData1, ReadData2, ReadData3;
wire[31:0] Result, ExtImm, SrcB, ALUResult
//wire[31:0] PCPlus4, PCBranch, pctmp;
wire[3:0] ALUOp, ALUFlags;
wire[1:0] RegSrc, ImmSrc;
wire PCSrc, RegWrite, MemWrite, MemtoReg, ALUSrc, Svalue;
//wire[31:0] NextPC;
assign ReadAddr1 = IF_ID_reg_inst[19:16];
assign ReadAddr2 = IF_ID_reg_inst[3:0];
assign WriteAddr = IF_ID_reg_inst[15:12];
assign memwrite = MemWrite;
assign memread = 'b1;
assign writedata = ReadData3;
wire[31:0] pctmp2;
wire[31:0] NextPC;
ctrlSig _ctrlSig(
.NZCV(NZCV), .cond(IF_ID_reg_inst[31:28]), .op(IF_ID_reg_inst[27:26]), .funct(IF_ID_reg_inst[25:20]), .ALUOp(ALUOp), .ImmSrc(ImmSrc), .RegSrc(RegSrc),
.PCSrc(PCSrc), .RegWrite(RegWrite), .MemWrite(MemWrite), .MemtoReg(MemtoReg), .ALUSrc(ALUSrc), .Svalue(Svalue));
RegisterFile _RegisterFile( .clk(clk), .reset(reset), .we(RegWrite), .RegSrc(RegSrc), .addr1(ReadAddr1), .addr2(ReadAddr2), .addr3(WriteAddr),
.waddr(WriteAddr), .wdata(Result), .pcin(NextPC), .data1(ReadData1), .data2(ReadData2), .data3(ReadData3), .pcout(pctmp2));
ExtendMUX _ExtendMUX( .in(inst[23:0]), .ImmSrc(ImmSrc), .ExtImm(ExtImm) );
assign pctmp2 = pctmp;
always @ (negedge clk) begin
ID_EX_reg_reset <= IF_ID_reg_reset;
ID_EX_reg_ALUOp <= ALUOp;
ID_EX_reg_ImmSrc <= ImmSrc;
ID_EX_reg_RegSrc <= RegSrc;
ID_EX_reg_PCSrc <= PCSrc;
ID_EX_reg_RegWrite <= RegWrite;
ID_EX_reg_MemWrite <= MemWrite;
ID_EX_reg_MemtoReg <= MemtoReg;
ID_EX_reg_ALUSrc <= ALUSrc;
ID_EX_reg_Svalue <= Svalue;
ID_EX_reg_Readdata1 <= ReadData1;
ID_EX_reg_Readdata2 <= ReadData2;
ID_EX_reg_Readdata3 <= ReadData3;
//ID_EX_reg_pcout <= pctmp;
ID_EX_reg_ExtImm <= ExtImm;
//ID_EX_reg_PCPlus4 <= IF_ID_reg_PCPlus4;
ID_EX_reg_NZCV_Flags <= NZCV_Flags;
ID_EX_reg_WriteAddr <= WriteAddr;
end
endmodule
module EXstage(
input clk,
//input pctmp,
input ID_EX_reg_reset,
input[3:0] ID_EX_reg_ALUOp,
input[1:0] ID_EX_reg_ImmSrc,
input[1:0] ID_EX_reg_RegSrc,
input ID_EX_reg_PCSrc,
input ID_EX_reg_RegWrite,
input ID_EX_reg_MemWrite,
input ID_EX_reg_MemtoReg,
input ID_EX_reg_ALUSrc,
input ID_EX_reg_Svalue,
input[31:0] ID_EX_reg_Readdata1,
input[31:0] ID_EX_reg_Readdata2,
input[31:0] ID_EX_reg_Readdata3,
//input[31:0] ID_EX_reg_pcout,
input[31:0] ID_EX_reg_ExtImm,
//input[31:0] ID_EX_reg_PCPlus4,
input[3:0] ID_EX_reg_WriteAddr,
input[3:0] ID_EX_reg_NZCV_Flags,
output reg[31:0] EX_MEM_reg_ALUResult,
output reg EX_MEM_reg_RegWrite,
output reg EX_MEM_reg_MemWrite,
output reg EX_MEM_reg_MemtoReg,
//output reg[31:0] EX_MEM_reg_NextPC,
output reg[31:0] EX_MEM_reg_memaddr,
output reg[31:0] EX_MEM_reg_Readdata3,
output reg[3:0] EX_MEM_reg_WriteAddr,
output[3:0] EX_NZCV
);
wire[31:0] SrcB;
wire[31:0] ALUResult;
assign SrcB = (ID_EX_reg_ALUSrc == 1'b0) ? ID_EX_reg_Readdata2 : ID_EX_reg_ExtImm;
wire[3:0] ALUFlags;
ALU32bit _ALU32bit( .SrcA(ID_EX_reg_Readdata1), .SrcB(SrcB), .ALUOp(ID_EX_reg_ALUOp), .ALUFlags(ALUFlags), .ALUResult(EX_MEM_ALUResult) );
wire[31:0] memaddr;
assign memaddr = ALUResult;
reg[3:0] NZCV;
//CondUnit
always @(posedge clk) begin
if (reset) NZCV = 4'b0000;
else NZCV = (ID_EX_reg_Svalue == 1'b1) ? ALUFlags : ID_EX_reg_NZCV_Flags;
end
assign EX_NZCV = NZCV;
//wire[31:0] PCBranch;
//wire[31:0] NextPC;
//assign PCBranch = pctmp + ID_EX_reg_ExtImm + 32'd8;
//assign NextPC = (ID_EX_reg_PCSrc == 1'b0) ? ID_EX_reg_PCPlus4 : PCBranch;
always @(negedge clk) begin
EX_MEM_ALUResult <= ALUResult;
EX_MEM_reg_RegWrite <= ID_EX_reg_RegWrite;
EX_MEM_reg_MemWrite <= ID_EX_reg_MemWrite;
EX_MEM_reg_MemtoReg <= ID_EX_reg_MemtoReg;
//EX_MEM_NextPC <= NextPC;
EX_MEM_reg_memaddr <= memaddr;
EX_MEM_reg_Readdata3 <= ID_EX_reg_Readdata3;
end
endmodule
module MEMstage(
input clk,
input[31:0] writedata, //armreduced output wire
input[31:0] readdata, //armreduced input wire
input memread, //armreduced output wire
input memwrite, //armreduced output wire
input[31:0] memaddr, //armreduced output wire
input[31:0] EX_MEM_reg_ALUResult,
input EX_MEM_reg_RegWrite,
input EX_MEM_reg_MemWrite,
input EX_MEM_reg_MemtoReg,
input[31:0] EX_MEM_reg_Readdata3,
input[3:0] EX_MEM_reg_WriteAddr,
output MEM_memread,
output MEM_memwrite,
output[31:0] MEM_writedata,
output[31:0] MEM_memaddr,
output reg MEM_WB_reg_RegWrite,
output reg MEM_WB_reg_MemtoReg,
output reg[31:0] MEM_WB_reg_writeaddr,
output reg[31:0] MEM_WB_reg_readdata,
output reg[31:0] MEM_WB_reg_ALUResult
);
assign memwrite = EX_MEM_reg_MemWrite;
assign memread = 1'b1;
assign memaddr = EX_MEM_ALUResult;
assign writedata = EX_MEM_reg_Readdata3;
always @(negedge clk) begin
MEM_WB_reg_RegWrite <= EX_MEM_reg_MemWrite;
MEM_WB_reg_MemtoReg <= EX_MEM_reg_MemtoReg;
MEM_WB_reg_WriteAddr <= EX_MEM_reg_WriteAddr;
MEM_WB_reg_readdata <= readdata;
MEM_WB_reg_ALUResult <= EX_MEM_reg_ALUResult;
end
endmodule
module WBstage(
input clk,
output MEM_WB_memwrite_out,
output reg[31:0] MEM_WB_memread_out,
output[31:0] MEM_WB_reg_memaddr_out,
output reg[31:0] MEM_WB_reg_readdata_out,
output reg[31:0] MEM_WB_reg_ALUResult
);
//assign Result = (MemtoReg == 1'b0) ? ALUResult : readdata;
endmodule
module armreduced(
input clk,
input reset,
output[31:0] pc,
input[31:0] inst,
input nIRQ,
output[3:0] be,
output[31:0] memaddr,
output memwrite,
output memread,
output[31:0] writedata,
input[31:0] readdata
);
assign be = 4'b1111;
wire IF_ID_reg_reset;
wire[31:0] IF_ID_reg_inst;
wire[31:0] IF_ID_reg_PCPlus4;
//wire[31:0] pctmp;
wire[31:0] NextPC;
wire[31:0] pctmp;
IFstage(.clk(clk),
.inst(inst),
.reset(reset),
//.pc(pc),
.IF_ID_reg_inst(IF_ID_reg_inst),
//.IF_ID_reg_PCPlus4(IF_ID_reg_PCPlus4),
.IF_ID_reg_reset(IF_ID_reg_reset),
//.IF_ID_reg_pctmp(pctmp));
wire ID_EX_reg_reset;
wire[3:0] ID_EX_reg_ALUOp;
wire[1:0] ID_EX_reg_ImmSrc;
wire[1:0] ID_EX_reg_RegSrc;
wire ID_EX_reg_PCSrc;
wire ID_EX_reg_RegWrite;
wire ID_EX_reg_MemWrite;
wire ID_EX_reg_MemtoReg;
wire ID_EX_reg_ALUSrc;
wire ID_EX_reg_Svalue;
wire[31:0] ID_EX_reg_Readdata1;
wire[31:0] ID_EX_reg_Readdata2;
wire[31:0] ID_EX_reg_Readdata3;
//wire[31:0] ID_EX_reg_pcout;
wire[31:0] ID_EX_reg_ExtImm;
//wire[31:0] ID_EX_reg_PCPlus4;
wire[3:0] ID_EX_reg_WriteAddr;
wire[3:0] WriteAddr;
wire[3:0] NZCV_Flags;
IDstage(.clk(clk),
.NZCV_Flags(NZCV_Flags),
.IF_ID_reg_reset(IF_ID_reg_reset),
.IF_ID_reg_inst(IF_ID_reg_inst),
//.IF_ID_reg_PCPlus4(IF_ID_reg_PCPlus4),
//.IF_ID_reg_pctmp(IF_ID_reg_pctmp),
.WriteAddr(WriteAddr),
.NextPC(NextPC),
.pctmp(pctmp),
.ID_EX_reg_reset(ID_EX_reg_reset),
.ID_EX_reg_ALUOp(ID_EX_reg_ALUOp),
.ID_EX_reg_ImmSrc(ID_EX_reg_ImmSrc),
.ID_EX_reg_RegSrc(ID_EX_reg_RegSrc),
.ID_EX_reg_PCSrc(ID_EX_reg_PCSrc),
.ID_EX_reg_RegWrite(ID_EX_reg_RegWrite),
.ID_EX_reg_MemWrite(ID_EX_reg_MemWrite),
.ID_EX_reg_MemtoReg(ID_EX_reg_MemtoReg),
.ID_EX_reg_ALUSrc(ID_EX_reg_ALUSrc),
.ID_EX_reg_Svalue(ID_EX_reg_Svalue),
.ID_EX_reg_Readdata1(ID_EX_reg_Readdata1),
.ID_EX_reg_Readdata2(ID_EX_reg_Readdata2),
.ID_EX_reg_Readdata3(ID_EX_reg_Readdata3),
//.ID_EX_reg_pcout(ID_EX_reg_pcout),
.ID_EX_reg_ExtImm(ID_EX_reg_ExtImm),
.ID_EX_reg_WriteAddr(ID_EX_reg_WriteAddr),
//.ID_EX_reg_PCPlus4(ID_EX_reg_PCPlus4)
);
wire[31:0] EX_MEM_reg_ALUResult;
wire RegWrite, MemWrite, MemtoReg;
wire[31:0] EX_MEM_reg_NextPC;
wire[31:0] EX_MEM_reg_memaddr;
wire[31:0] EX_MEM_reg_Readdata3;
wire[3:0] EX_MEM_reg_WriteAddr;
EXstage(
.clk(clk),
//.pctmp(pctmp),
.ID_EX_reg_reset(ID_EX_reg_reset),
.ID_EX_reg_ALUOp(ID_EX_reg_ALUOp),
.ID_EX_reg_ImmSrc(ID_EX_reg_ImmSrc),
.ID_EX_reg_RegSrc(ID_EX_reg_RegSrc),
.ID_EX_reg_PCSrc(ID_EX_reg_PCSrc),
.ID_EX_reg_RegWrite(ID_EX_reg_RegWrite),
.ID_EX_reg_MemWrite(ID_EX_reg_MemWrite),
.ID_EX_reg_MemtoReg(ID_EX_reg_MemtoReg),
.ID_EX_reg_ALUSrc(ID_EX_reg_ALUSrc),
.ID_EX_reg_Svalue(ID_EX_reg_Svalue),
.ID_EX_reg_Readdata1(ID_EX_reg_Readdata1),
.ID_EX_reg_Readdata2(ID_EX_reg_Readdata2),
.ID_EX_reg_Readdata3(ID_EX_reg_Readdata3),
//.ID_EX_reg_pcout(ID_EX_reg_pcout),
.ID_EX_reg_ExtImm(ID_EX_reg_ExtImm),
//.ID_EX_reg_PCPlus4(ID_EX_reg_PCPlus4),
.ID_EX_reg_WriteAddr(ID_EX_reg_WriteAddr),
.ID_EX_reg_NZCV_Flags(NZCV_Flags),
.EX_MEM_reg_ALUResult(EX_MEM_reg_ALUResult),
.EX_MEM_reg_RegWrite(EX_MEM_reg_RegWrite),
.EX_MEM_reg_MemWrite(EX_MEM_reg_MemWrite),
.EX_MEM_reg_MemtoReg(EX_MEM_reg_MemtoReg),
//.EX_MEM_NextPC(EX_MEM_NextPC),
.EX_MEM_memaddr(EX_MEM_memaddr),
.EX_MEM_reg_WriteAddr(EX_MEM_reg_WriteAddr),
.EX_NZCV(NZCV_Flags)
);
wire MEM_WB_reg_RegWrite;
wire MEM_WB_reg_MemtoReg;
wire[31:0] MEM_WB_reg_readdata_out;
wire[31:0] MEM_WB_reg_ALUResult;
wire[3:0] MEM_WB_reg_WriteAddr;
MEMstage(
.clk(clk),
.writedata(writedata),
.readdata(readdata),
.memread(memread),
.memwrite(memwrite),
.memaddr(memaddr),
.EX_MEM_reg_ALUResult(EX_MEM_reg_ALUResult),
.EX_MEM_reg_RegWrite(EX_MEM_reg_RegWrite),
.EX_MEM_reg_MemWrite(EX_MEM_reg_MemWrite),
.EX_MEM_reg_MemtoReg(EX_MEM_reg_MemtoReg),
.EX_MEM_reg_Readdata3(EX_MEM_reg_Readdata3),
.EX_MEM_reg_WriteAddr(EX_MEM_reg_WriteAddr),
.memwrite(memwrite),
.memread(memread),
.MEM_WB_memwrite_out(writedata),
.MEM_WB_memread_out(MEM_WB_memread_out),
.MEM_WB_reg_memaddr_out(memaddr),
.MEM_WB_reg_readdata_out(MEM_WB_reg_readdata_out),
.MEM_WB_reg_ALUResult(MEM_WB_reg_ALUResult)
);
endmodule
/*
//IF_ID_reg, ID_EX_reg, EX_MEM_reg, MEM_WB_reg
//IF stage
assign PCPlus4 = pctmp + 32'd4;
IF_ID_reg(.clk(clk), .PCPlus4(PCPlus4), .pc(pc), .IF_ID_reg_PCPlus4(IF_ID_reg_PCPlus4), .IF_ID_reg_inst(IF_ID_reg_inst));
always @ (posedge clk) begin
IF_ID_reg_PCPlus4 <= PCPlus4;
IF_ID_reg_inst <= pc;
end
//ID stage
ctrlSig _ctrlSig(
.NZCV(NZCV), .cond(IF_ID_reg_inst[31:28]), .op(IF_ID_reg_inst[27:26]), .funct(IF_ID_reg_inst[25:20]), .ALUOp(ALUOp), .ImmSrc(ImmSrc), .RegSrc(RegSrc),
.PCSrc(PCSrc), .RegWrite(RegWrite), .MemWrite(MemWrite), .MemtoReg(MemtoReg), .ALUSrc(ALUSrc), .Svalue(Svalue));
ExtendMUX _ExtendMUX( .in(inst[23:0]), .ImmSrc(ImmSrc), .ExtImm(ExtImm) );
assign PCBranch = pctmp + ExtImm + 32'd8;
assign NextPC = (PCSrc == 1'b0) ? IF_ID_reg_PCPlus4 : PCBranch;
assign ReadAddr1 = inst[19:16];
assign ReadAddr2 = inst[3:0];
assign WriteAddr = inst[15:12];
RegisterFile _RegisterFile( .clk(clk), .reset(reset), .we(RegWrite), .RegSrc(RegSrc), .addr1(ReadAddr1), .addr2(ReadAddr2), .addr3(WriteAddr),
.waddr(WriteAddr), .wdata(Result), .pcin(NextPC), .data1(ReadData1), .data2(ReadData2), .data3(ReadData3), .pcout(pctmp));
assign writedata = ReadData3;
reg[3:0] ID_EX_reg_ALUOp;
reg[1:0] ID_EX_reg_ImmSrc;
reg[1:0] ID_EX_reg_RegSrc;
reg ID_EX_reg_PCSrc;
reg ID_EX_reg_RegWrite;
reg ID_EX_reg_MemWrite;
reg ID_EX_reg_MemtoReg;
reg ID_EX_reg_ALUSrc;
reg ID_EX_reg_Svalue;
reg[31:0] ID_EX_reg_NextPC;
reg[31:0] ID_EX_reg_ExtImm;
reg[31:0] ID_EX_reg_regout1;
reg[31:0] ID_EX_reg_regout2;
reg[31:0] ID_EX_reg_pc;
always @ (posedge clk) begin
ID_EX_reg_ALUOp <= ALUOp;
ID_EX_reg_ImmSrc <= ImmSrc;
ID_EX_reg_RegSrc <= RegSrc;
ID_EX_reg_PCSrc <= PCSrc;
ID_EX_reg_RegWrite <= RegWrite;
ID_EX_reg_MemWrite <= MemWrite;
ID_EX_reg_MemtoReg <= MemtoReg;
ID_EX_reg_ALUSrc <= ALUSrc;
ID_EX_reg_Svalue <= Svalue;
ID_EX_reg_ExtImm <= ExtImm;
ID_EX_reg_regout1 <= ReadData1;
ID_EX_reg_regout2 <= ReadData2;
ID_EX_reg_pc <= pctmp;
ID_EX_reg_NextPC <= NextPC;
end
//EX stage
assign SrcB = (ID_EX_reg_ALUSrc == 1'b0) ? ID_EX_reg_regout2 : ID_EX_reg_ExtImm;
ALU32bit _ALU32bit( .SrcA(ID_EX_reg_regout1), .SrcB(SrcB), .ALUOp(ID_EX_reg_ALUOp), .ALUFlags(ALUFlags), .ALUResult(ALUResult) );
reg[3:0] NZCV;
reg[31:0] EX_MEM_reg_ALUResult;
reg[3:0] EX_MEM_reg_ALUFlags;
reg[31:0] EX_MEM_reg_pc;
always @ (posedge clk) begin
EX_MEM_reg_ALUResult <= ALUResult;
EX_MEM_reg_ALUFlags <= ALUFlags;
EX_MEM_reg_pc <= ID_EX_reg_pc;
if (reset) NZCV = 4'b0000;
else NZCV = (Svalue == 1'b1) ? ALUFlags : NZCV; //Svalue : FlagWriteE
end
//MEM stage
assign memwrite = MemWrite;
assign memread = 'b1;
assign memaddr = ALUResult;
always @ (posedge clk) begin
end
//WB stage
//assign Result = (MemtoReg == 1'b0) ? ALUResult : readdata;
//RegisterFile _RegisterFile( .clk(clk), .reset(reset), .we(RegWrite), .RegSrc(RegSrc), .addr1(ReadAddr1), .addr2(ReadAddr2), .addr3(WriteAddr),
// .waddr(WriteAddr), .wdata(Result), .pcin(NextPC), .data1(ReadData1), .data2(ReadData2), .data3(ReadData3), .pcout(pctmp));
always @ (posedge clk) begin
end
*/
/*
wire[31:0] EX_MEM_reg_ALUResult;
//wire RegWrite, MemWrite, MemtoReg;
wire[31:0] EX_MEM_reg_NextPC;
wire[31:0] EX_MEM_reg_memaddr;
wire[31:0] EX_MEM_reg_Readdata3;
wire[3:0] EX_MEM_reg_WriteAddr;
//wire[31:0] SrcB;
//wire[31:0] ALUResult;
assign SrcB = (ID_EX_reg_ALUSrc == 1'b0) ? ID_EX_reg_Readdata2 : ID_EX_reg_ExtImm;
//wire[3:0] ALUFlags;
ALU32bit _ALU32bit( .SrcA(ID_EX_reg_Readdata1), .SrcB(SrcB), .ALUOp(ID_EX_reg_ALUOp), .ALUFlags(ALUFlags), .ALUResult(EX_MEM_ALUResult) );
//wire[31:0] memaddr;
assign memaddr = ALUResult;
wire[3:0] ID_EX_reg_NZCV_Flags;
reg[3:0] NZCV;
//CondUnit
always @(posedge clk) begin
if (reset) NZCV = 4'b0000;
else NZCV = (ID_EX_reg_Svalue == 1'b1) ? ALUFlags : ID_EX_reg_NZCV_Flags;
end
assign EX_NZCV = NZCV;
EXstage(
.clk(clk),
.ID_EX_reg_reset(ID_EX_reg_reset),
.ID_EX_reg_ALUOp(ID_EX_reg_ALUOp),
.ID_EX_reg_ImmSrc(ID_EX_reg_ImmSrc),
.ID_EX_reg_RegSrc(ID_EX_reg_RegSrc),
.ID_EX_reg_PCSrc(ID_EX_reg_PCSrc),
.ID_EX_reg_RegWrite(ID_EX_reg_RegWrite),
.ID_EX_reg_MemWrite(ID_EX_reg_MemWrite),
.ID_EX_reg_MemtoReg(ID_EX_reg_MemtoReg),
.ID_EX_reg_ALUSrc(ID_EX_reg_ALUSrc),
.ID_EX_reg_Svalue(ID_EX_reg_Svalue),
.ID_EX_reg_Readdata1(ID_EX_reg_Readdata1),
.ID_EX_reg_Readdata2(ID_EX_reg_Readdata2),
.ID_EX_reg_Readdata3(ID_EX_reg_Readdata3),
.ID_EX_reg_ExtImm(ID_EX_reg_ExtImm),
.ID_EX_reg_WriteAddr(ID_EX_reg_WriteAddr),
.ID_EX_reg_NZCV_Flags(NZCV_Flags),
.ALUResult(ALUResult),
.EX_MEM_reg_ALUResult(EX_MEM_reg_ALUResult),
.EX_MEM_reg_RegWrite(EX_MEM_reg_RegWrite),
.EX_MEM_reg_MemWrite(EX_MEM_reg_MemWrite),
.EX_MEM_reg_MemtoReg(EX_MEM_reg_MemtoReg),
.EX_MEM_memaddr(EX_MEM_memaddr),
.EX_MEM_reg_WriteAddr(EX_MEM_reg_WriteAddr),
.EX_NZCV(NZCV_Flags)
);
wire MEM_WB_reg_RegWrite;
wire MEM_WB_reg_MemtoReg;
wire[31:0] MEM_WB_reg_readdata_out;
wire[31:0] MEM_WB_reg_ALUResult;
wire[3:0] MEM_WB_reg_WriteAddr;
assign memwrite = EX_MEM_reg_MemWrite;
assign memread = 1'b1;
assign memaddr = EX_MEM_ALUResult;
assign writedata = EX_MEM_reg_Readdata3;
MEMstage(
.clk(clk),
.writedata(writedata),
.readdata(readdata),
//.memread(memread),
//.memwrite(memwrite),
.EX_MEM_memaddr(EX_MEM_memaddr),
.EX_MEM_reg_ALUResult(EX_MEM_reg_ALUResult),
.EX_MEM_reg_RegWrite(EX_MEM_reg_RegWrite),
.EX_MEM_reg_MemWrite(EX_MEM_reg_MemWrite),
.EX_MEM_reg_MemtoReg(EX_MEM_reg_MemtoReg),
.EX_MEM_reg_Readdata3(EX_MEM_reg_Readdata3),
.EX_MEM_reg_WriteAddr(EX_MEM_reg_WriteAddr),
.memaddr(memaddr),
//.memwrite(memwrite),
//.memread(memread),
.MEM_WB_memwrite_out(writedata),
.MEM_WB_memread_out(MEM_WB_memread_out),
//.MEM_WB_reg_memaddr_out(memaddr),
.MEM_WB_reg_readdata_out(MEM_WB_reg_readdata_out),
.MEM_WB_reg_ALUResult(MEM_WB_reg_ALUResult)
);
*/
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